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1. #8 BIT PARALLEL TO SERIAL CONVERTER CIRCUIT DIAGRAM GENERATOR#
2. #8 BIT PARALLEL TO SERIAL CONVERTER CIRCUIT DIAGRAM SERIAL#

#8 BIT PARALLEL TO SERIAL CONVERTER CIRCUIT DIAGRAM SERIAL#

The holding register loads and stores n-bit (n is an integer) parallel input digital data with a load input, and then the shift register receives the stored data in parallel from the holding register to shift n-bit serial signal on a bit by bit basis with a shift clock signal which has a higher rate than the input digital data. (See, for example, pages 4-9 of "Technical Aspects of Data Communication" (in Japanese) published by CQ Publishing Company, on Apr. This invention relates to an improvement for a a parallel/serial converter which converts parallel signal sequence into a serial signal sequence.Ī parallel/serial converter of this type has been used for an interface which converts parallel data from a computer or a communication system to serial data and a multiplexer which multiplexes a plurality of data sequences from plural channels.Ī prior art parallel/serial converter comprises a parallel input/serial output shift register and a holding register connected to the parallel input side of the shift register as a buffer store means. The parallel to serial converter of claim 3, further comprising delay circuit means for delaying said second timing pulses relative to said first timing pulses. The parallel to serial converter to claim 1, wherein said timing generating means comprises an oscillator for producing said shift pulses, and clock divider means for producing said first and second timing pulses from an output of said oscillator.Ĥ.

#8 BIT PARALLEL TO SERIAL CONVERTER CIRCUIT DIAGRAM GENERATOR#

The parallel to serial converter of claim 1, wherein said timing generator means is further effective for generating a load pulse for loading into said shift register means said first n bit and third n×m bit parallel data, said load pulse being timed with said first timing pulses.ģ.

Timing generating means for generating said first timing pulses, m sets of second timing pulses and said shift pulses, said shift pulses having a pulse rate which permits serial shifting of said first and third data from said shift register within a period corresponding to a repetition rate of said first timing pulses.Ģ. Shift register means coupled to said first and third latch means and responsive to said first n bit parallel data and said third n×m bit parallel data for registering said first and third parallel data and for shifting said first and third data in response to shift pulses and Third latch means responsive to said first timing pulses for latching said m sets of second n bit parallel data to produce third n×m bit parallel data Second latch means comprising m (m being an integer greater than one) latches connected to said n bit data lines for latching in parallel said n bit parallel input data one after another in response to m sets of second timing pulses, each of said second timing pulses having a clock rate one/(m+1)th of said main clock rate and said first timing pulses and successive ones of said second timing pulses being delayed relative to each other by one clock period of said main clock rate to produce m sets of second n bit parallel data, said first timing pulses and said m sets of second timing pulses being sequentially supplied to said first and second latch means respectively

A parallel to serial converter for converting n bit (n being an integer) parallel input data provided on n bit data lines at a main clock rate into a serial data stream, said parallel to serial converter comprising:įirst latch means connected to said n bit data lines and responsive to first timing pulses for latching said n bit parallel input data to produce first n bit parallel data, said first timing pulses having a clock rate one/(m+1)th of said main clock rate